106 lines
3.1 KiB
Plaintext
106 lines
3.1 KiB
Plaintext
* ============================================================
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* SY8368AQQC - Behavioral SPICE Model
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* Silergy 8A Synchronous Step-Down Regulator
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* For use with KiCad / ngspice
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* ============================================================
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*
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* Behavioral model capturing key electrical characteristics:
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* - Voltage-mode PWM switching at 800kHz
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* - Synchronous rectification with RDS(on) losses
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* - Internal 0.6V reference
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* - Enable / UVLO (3.9V)
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* - Internal 3.3V LDO on VCC pin
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* - Power Good open-drain output
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* - Soft start (~600us)
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*
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* Limitations:
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* - Simplified feedback loop (no detailed compensation)
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* - No thermal modeling
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* - No detailed gate drive timing / dead time
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* - ILMT current limiting not enforced
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*
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* Subcircuit pins match QFN-12 package pinout 1:1:
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* Pin 1 = GND1
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* Pin 2 = LX
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* Pin 3 = GND2
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* Pin 4 = IN1
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* Pin 5 = IN2
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* Pin 6 = IN3
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* Pin 7 = BS
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* Pin 8 = VCC
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* Pin 9 = FB
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* Pin 10 = ILMT
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* Pin 11 = PG
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* Pin 12 = EN
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*
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* Usage:
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* X1 GND1 LX GND2 IN1 IN2 IN3 BS VCC FB ILMT PG EN SY8368AQQC
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*
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* ============================================================
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.subckt SY8368AQQC GND1 LX GND2 IN1 IN2 IN3 BS VCC FB ILMT PG EN
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* --- Tie duplicate pins together internally ---
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R_gnd12 GND1 GND2 0.001
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R_in12 IN1 IN2 0.001
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R_in23 IN2 IN3 0.001
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* --- Use GND1 as the internal ground reference, IN1 as VIN ---
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* --- Parameters ---
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.param Fsw=800k
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.param Tperiod={1/Fsw}
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.param Vref=0.6
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.param Rdson_hs=20m
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.param Rdson_ls=10m
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.param Vcc_int=3.3
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.param Vuvlo=3.9
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* --- Internal 3.3V LDO (VCC pin) ---
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B_vcc VCC GND1 V = V(IN1,GND1) > Vuvlo ? Vcc_int : 0
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* --- Enable and UVLO logic ---
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B_en en_int GND1 V = (V(EN,GND1) > 0.8 && V(IN1,GND1) > Vuvlo) ? 1 : 0
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* --- Soft Start Ramp ---
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* RC charge toward 1V, ~600us time constant
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R_ss1 ss_drv ss_node 1k
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C_ss ss_node GND1 600n IC=0
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B_ss_src ss_drv GND1 V = V(en_int,GND1) > 0.5 ? 1.0 : 0
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* Effective reference: min of soft-start ramp and 0.6V
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B_vref vref_eff GND1 V = min(V(ss_node,GND1), Vref)
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* --- Error Amplifier (behavioral) ---
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* High-gain comparison: FB vs reference -> duty cycle
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B_ea ea_out GND1 V = V(en_int,GND1) > 0.5 ? min(max(200*(V(vref_eff,GND1) - V(FB,GND1)) + 0.25, 0.0), 0.95) : 0
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* --- PWM Sawtooth + Comparator ---
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V_saw saw_node GND1 PULSE(0 1 0 {Tperiod} 1n 1n {Tperiod})
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B_pwm pwm_out GND1 V = V(ea_out,GND1) > V(saw_node,GND1) ? 5 : 0
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* --- Power Stage (Synchronous Buck) ---
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* High-side switch: VIN to LX when PWM high
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S_hs IN1 LX pwm_out GND1 SW_HS
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.model SW_HS SW VT=2.5 VH=0.5 RON={Rdson_hs} ROFF=10MEG
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* Low-side needs inverted control
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B_pwm_inv pwm_inv GND1 V = 5.0 - V(pwm_out,GND1)
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S_ls LX GND1 pwm_inv GND1 SW_LS
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.model SW_LS SW VT=2.5 VH=0.5 RON={Rdson_ls} ROFF=10MEG
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* --- Bootstrap ---
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R_bs_ext BS bs_mid 1
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B_bs_chg bs_mid GND1 V = V(LX,GND1) + Vcc_int
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* --- Power Good (open-drain output) ---
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* PG is open drain: LOW when FB is outside 90%-120% of Vref
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B_pg_ctrl pg_ctrl GND1 V = (V(FB,GND1) < 0.54 || V(FB,GND1) > 0.72) ? 5 : 0
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S_pg PG GND1 pg_ctrl GND1 SW_PG
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.model SW_PG SW VT=2.5 VH=0.5 RON=50 ROFF=10MEG
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* --- ILMT pin (netlist compatibility) ---
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R_ilmt ILMT GND1 1MEG
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.ends SY8368AQQC
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